The present disclosure relates to a semiconductor device, a method of manufacturing such a semiconductor device, and an antenna switch module, and more specifically to a semiconductor device having a radio-frequency switch device on an SOI (Silicon on Insulator) substrate, a method of manufacturing such a semiconductor device, and an antenna switch module.
In recent years, for antenna switch devices, FETs (Field-Effect Transistors) of compound semiconductors (for example, GaAs) that allow complicated switch circuits with reduced power consumption to be manufactured easily have been utilized.
However, such compound semiconductor FETs have been disadvantageous in that they may be expensive in themselves, and they may involve high manufacturing costs for a reason that it is necessary to incorporate peripheral circuits that are fabricated on a separate chip as a module, or for any other reason. It is to be noted that examples of the peripheral circuits may include a DC-DC converter, an IPD (Integrated Passive Device), and the like.
Consequently, in recent years, the development of antenna switch devices using an SOI substrate that enables mixed mounting with a DC-DC converter circuit that is a silicon-based device to be used as a peripheral circuit has been actively carried forward. The SOI substrate has an advantage of being capable of reducing any parasitic capacitance (depletion layer capacitance) that may be caused due to PN-junction, which ensures to achieve the high-performance antenna switch devices equivalent to compound-based semiconductors.
However, the SOI substrate has a disadvantage of deterioration in the electrical characteristics that may be caused due to self-heating of MOS transistors. This self-heating is typically a Joule heat resulting from channel resistances, being generated by a current flowing through a channel region when an FET is put in ON state.
In particular, MOS transistors that are fabricated on the SOI substrate are separated from silicon of a support substrate by means of a material (for example, silicon oxide) with the thermal conductivity lower than that of silicon by two orders of magnitude or more, and thus any heat arising at a channel region may be hard to be dissipated due to an effect of silicon oxide directly underneath channels, causing the heat dissipation characteristics to be further deteriorated. It is to be noted that the thermal conductivity of silicon is about 144 [W/(m·K)], while the thermal conductivity of silicon oxide is about 1.1 [W/(m·K)].
Examples of technologies for solutions to disadvantages as described above may include some technologies that are disclosed in Japanese Unexamined Patent Application Publication No. H06-029376, Japanese Unexamined Patent Application Publication No. H05-343667, and the nonpatent document 1: A. Botula, et al., “A Thin-film SOI 180 nm CMOS RF Switch Technology”, Silicon Monolithic Integrated Circuits in RF Systems, 2009.
An integrated circuit device that is described in Japanese Unexamined Patent Application Publication No. H06-029376 includes an n-type semiconductor layer to be bonded via a silicon oxide film on a semiconductor support substrate, wherein a backside contact trench that is formed in a manner of running through the silicon oxide film from the backside of the semiconductor support substrate to reach the semiconductor layer is formed at a semiconductor support substrate region on the underside of this semiconductor layer, and a metallic conductive member is embedded into this backside contact trench. Through this metallic conductive member, any heat arising on the semiconductor layer is dissipated.
However, in the technology disclosed in Japanese Unexamined Patent Application Publication No. H06-029376, a large number of backside contact trenches may be necessary when a spacing area for switch devices that are formed on the semiconductor layer is large. Accordingly, such a technology is disadvantageous in that rewiring from the semiconductor support substrate side may be difficult for a portion of the backside contact trenches, which may make it difficult to reduce a size.
In the technology disclosed in the nonpatent document 1, radio-frequency switch elements (source region, drain region, gate oxide film, source electrode, gate electrode, and drain electrode) are formed on an SOI substrate where an insulating film and a semiconductor layer are formed in order of precedence on a semiconductor substrate, wherein trenches running through an area as far as the semiconductor substrate are formed at the periphery of the radio-frequency switch elements, and a crystal defect layer as a damage layer is formed on the semiconductor substrate in a manner of, for example, implanting argon onto a semiconductor substrate area at the bottom of the trenches using an ion implanting technique.
This crystal defect layer traps, that is, recombines any carriers arising within the semiconductor substrate when radio-frequency signals are applied, which prevents variation in the capacitance of the substrate to improve the harmonic distortion characteristics. Additionally, by forming an electrode running through the semiconductor substrate from the semiconductor layer, a potential of the substrate is fixed to further enhance the effectiveness of preventing variation in the capacitance of the substrate.
However, in the technology disclosed in the nonpatent document 1, a region (crystal defect layer as a damage layer) for trapping any carriers arising within the semiconductor substrate when radio-frequency signals are applied is not present directly beneath transistors, which makes it difficult to completely suppress variations of carriers.
Further, for a support substrate for the SOI substrate to be used for the radio-frequency switches, a substrate with quite high resistance values may be typically used, and thus there is a disadvantage that the intended effectiveness of an electrode running through the semiconductor layer and the semiconductor substrate for the purpose of fixing a substrate potential is reduced. In addition, there is also a disadvantage that manufacturing costs rise due to increased number of processes.
A method concerning improvements of deterioration in the electrical characteristics due to self-heating that is disclosed in Japanese Unexamined Patent Application Publication No. H06-029376 as described above, which adopts the backside contact for heat dissipation, dissipates any heat by means of the metallic conductive member. Further, a method concerning improvements of the harmonic distortion characteristics that is disclosed in the nonpatent document 1, which adopts the crystal defect layer on one side of the semiconductor substrate, prevents variation in the substrate capacitance by trapping, that is, recombining any carriers that are generated by a radio-frequency field by means of the crystal defect layer to suppress generation of the harmonic distortion.
However, in recent years, as technologies for achieving higher-powered outputs have been advanced, and the field intensity has been increasingly raised, it may be insufficient in some cases to provide the crystal defect layer on only one side of the semiconductor substrate. In such a case, an electron beam irradiation method that allows crystal defects to be introduced uniformly over a whole surface of the substrate may be helpful, although this has posed a disadvantage that the device characteristics vary due to the influence of a hole trap which is formed in a silicon oxide film.
Examples of disadvantages that have been found in the past may include drop in threshold voltages of n-channel MOSFETs, rise in threshold voltages of p-channel MOSFETs, and rise in polysilicon resistances that is caused due to introduction of crystal defects.
A technology for a solution to the disadvantage as described above is disclosed in Japanese Unexamined Patent Application Publication No. H05-343667.
A method of repeating electron beam irradiation and thermal treatment more than once that are applied to power device IGBTs (Insulated Gate Bipolar Transistors) is disclosed in Japanese Unexamined Patent Application Publication No. H05-343667. In this method, by changing the acceleration voltage and irradiation amount for the electron beam irradiation as well as temperature, time, and the like for the thermal treatment, it is possible to tailor a crystal defect layer and device characteristics to fit desired characteristics.